求助关于VHDL的 LOOP语法的用法，具体如下~

Question

各位大神们，小弟最近在学习VHDL 语言，在做一个具体案例的时候遇到一点问题，纠结了好几天了，问题如下：
给定一个1MHZ的CLK，要基于此CLK的和另外一个信号RST的基础上输出一个1ms的短脉冲，这个我该如何去做呀？程序怎么写？

Answer 1

如果要实现你所说的这些功能，完全不必使用到loop 这样复杂的语句。源代码&nbsp;alm 给你：-- Generated by Mentor Graphics' HDL Designer(TM) 2005.3 (Build 75)--LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;ENTITY pulse IS&nbsp; &nbsp;PORT(&nbsp;&nbsp; &nbsp; &nbsp; clk &nbsp; &nbsp; : IN &nbsp; &nbsp; std_logic;&nbsp; &nbsp; &nbsp; rst &nbsp; &nbsp; : IN &nbsp; &nbsp; std_logic;&nbsp; &nbsp; &nbsp; rst_rst : IN &nbsp; &nbsp; std_logic;&nbsp; &nbsp; &nbsp; output &nbsp;: OUT &nbsp; &nbsp;std_logic&nbsp; &nbsp;);-- DeclarationsEND pulse ;---- VHDL Architecture study7_2_lib.pulse.fsm---- Created:-- &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;by - PCHYKJUSER.UNKNOWN (TYL)-- &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;at - 18:24:10 2013-05-20---- Generated by Mentor Graphics' HDL Designer(TM) 2005.3 (Build 75)--LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;ARCHITECTURE fsm OF pulse IS&nbsp; &nbsp;-- Architecture Declarations&nbsp; &nbsp;SIGNAL count : integer RANGE 1000 DOWNTO 0; &nbsp;&nbsp; &nbsp;SIGNAL rsta0 : std_logic; &nbsp;&nbsp; &nbsp;SIGNAL rsta1 : std_logic; &nbsp;&nbsp; &nbsp;TYPE STATE_TYPE IS (&nbsp; &nbsp; &nbsp; hold,&nbsp; &nbsp; &nbsp; one_pulse&nbsp; &nbsp;);&nbsp; &nbsp;-- State vector declaration&nbsp; &nbsp;ATTRIBUTE state_vector : string;&nbsp; &nbsp;ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state";&nbsp; &nbsp;-- Declare current and next state signals&nbsp; &nbsp;SIGNAL current_state : STATE_TYPE;&nbsp; &nbsp;SIGNAL next_state : STATE_TYPE;&nbsp; &nbsp;-- Declare any pre-registered internal signals&nbsp; &nbsp;SIGNAL output_cld : std_logic ;BEGIN&nbsp; &nbsp;-----------------------------------------------------------------&nbsp; &nbsp;clocked_proc : PROCESS (&nbsp;&nbsp; &nbsp; &nbsp; clk,&nbsp; &nbsp; &nbsp; rst_rst&nbsp; &nbsp;)&nbsp; &nbsp;-----------------------------------------------------------------&nbsp; &nbsp;BEGIN&nbsp; &nbsp; &nbsp; IF (rst_rst = '0') THEN&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;current_state <= hold;&nbsp; &nbsp; &nbsp; ELSIF (clk'EVENT AND clk = '1') THEN&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;current_state <= next_state;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;count<=0;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;-- Combined Actions&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;CASE current_state IS&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; WHEN hold =>&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;output_cld<='0';&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;rsta0<=rst;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;rsta1<=rsta0;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; WHEN one_pulse =>&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;output_cld<='1';&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;count<=count+1;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; WHEN OTHERS =>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;NULL;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;END CASE;&nbsp; &nbsp; &nbsp; END IF;&nbsp; &nbsp;END PROCESS clocked_proc;&nbsp; &nbsp;-----------------------------------------------------------------&nbsp; &nbsp;nextstate_proc : PROCESS (&nbsp;&nbsp; &nbsp; &nbsp; count,&nbsp; &nbsp; &nbsp; current_state,&nbsp; &nbsp; &nbsp; rsta0,&nbsp; &nbsp; &nbsp; rsta1&nbsp; &nbsp;)&nbsp; &nbsp;-----------------------------------------------------------------&nbsp; &nbsp;BEGIN&nbsp; &nbsp; &nbsp; CASE current_state IS&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;WHEN hold =>&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; IF (rsta1='1' and &nbsp;rsta0='0') THEN&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;next_state <= one_pulse;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; ELSE&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;next_state <= hold;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; END IF;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;WHEN one_pulse =>&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; IF (count=999) THEN&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;next_state <= hold;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; ELSIF (count<999) THEN&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;next_state <= one_pulse;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; ELSE&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;next_state <= one_pulse;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; END IF;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;WHEN OTHERS =>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; next_state <= hold;&nbsp; &nbsp; &nbsp; END CASE;&nbsp; &nbsp;END PROCESS nextstate_proc;&nbsp; &nbsp;-- Concurrent Statements&nbsp; &nbsp;-- Clocked output assignments&nbsp; &nbsp;output <= output_cld;END fsm;可能对于小学生（adulteration）来说 用这种风格编写代码你可能会读不懂。&nbsp;但是养成良好的编写代码习惯是很重要的，此段代码我已经在 alter 公司的娱乐工具 quartus II 上仿真过了，无错。注意：输入 rst_rst 是复位信号，这个一定要有！&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;而 rst 就是你所提到的，所谓的控制信号。output 就是输出信号无误了，也就是由他输出 脉冲。 频率也是没错的，仿真的时候注意好等复位结束后才输入控制信号，控制信号是高电平有效。复位是 低电平。咱用的是这个软件编写的代码 &nbsp; FPGA advantage ,这种程度的代码编写过程不过是10分钟，不过很稀奇国内的&nbsp;greenhand 都没有学这玩意的倾向。