具体情况如下，是有关EDA设计的问题，麻烦大佬看看~

Question

我在做EDA设计时下面这个语句不能被综合请问怎么改？？
repeat（2）@（posedge clk）;
这个语句在下面这个程序段中
always@(state or x)
begin
case(state)
s0:if(x)
next_state=s1;
else
next_state=s0;
s1:begin
repeat(`Y2RDELAY)@(posedge clock);
next_state=s2;
end
s2:begin
repeat(`R2GDELAY)@(posedge clock); 
next_state=s3;
end 
s3:if(x)
next_state=s3;
else
next_state=s4;
s4:begin
repeat(`Y2RDELAY)@(posedge clock);
next_state=s0;
end
default:next_state=s0;
endcase
end
endmodule
repeat(`Y2RDELAY)@(posedge clock);
这条语句怎么替代

Answer 1

你也就是想让下面的语句执行2次对吧，可以用计数器实现。程序开始计数器初值赋0；比如说S2状态可以像下面这样写：s2:beginif(cnt==1)begincnt<=0;next_state<=S 3;endelsebegincnt<=cnt+1;next_state<=S2;endend

Answer 2

always@(state or x)这是个组合逻辑电路然后你在内部用 @(posedge clock)这是个时序逻辑电路你还是没理解代码与硬件映射的关系请参考标准状态机写法always@（posedge clock or negedge reset_n）beginif( !reset_n)CurrState <= 4'b0;elseCurrState <= NextState;endalways@(*) beginNextState = CurrState;case(CurrState)State0:if(...)NextState = State1;State1:if(...)NextState = State2;....default: ....;endcaseend