代码如下，关于错误提示在最后行，是关于交通灯的问题。求大佬帮忙看看~

Question

module traffic2(CLK,RESET,AG,AY,AR,BG,BY,BR,TC,UP,DOWN);
input CLK,RESET,UP,DOWN,TC;
output AG,AY,AR,BG,BY,BR;
reg AG,AY,AR,BG,BY,BR;
reg [3:0]Timer,Timer2,TimerY;
wire Timer1;
wire Ta,Tb,Ty;
reg St;
reg [1:0]CurrentState,NextState;
parameter S0=2'b00,S1=2'b01,S2=2'b11,S3=2'b10;
always@(posedge CLK or negedge RESET)
begin:statereg
if(~RESET) CurrentState<=S0;
else CurrentState<=NextState;
end
always@(CurrentState or Ta or Tb or Ty)
begin:fsm
case(CurrentState)
S0:begin
NextState=(~Ta)?S1:S0;
St=(~Ta)?1:0;
end
S1:begin
NextState=(~Ty)?S2:S1;
St=(~Ty)?1:0;
end
S2:begin
NextState=(~Tb)?S3:S2;
St=(~Tb)?1:0;
end
S3:begin
NextState=(~Ty)?S0:S3;
St=(~Ty)?1:0;
end
endcase
end
assign Timer1=9; 

always@(posedge CLK or posedge EN or negedge RESET or posedge TC )
begin:counter
if((EN)&&(Timer2==0))
begin:
Timer2<=Timer1;
Timer<=Timer1;
end
else if(~RESET)
begin:
Timer2<=Timer1;
Timer<=Timer1;
end
else if(TC)
begin:
if(UP)Timer2<=Timer2+1'b1;
else if(DOWN)Timer2<=Timer2-1'b1;
end
else if(St)Timer<=Timer2;
else Timer<=Timer-1;

end

assign Ta=Timer;
assign Tb=Timer;

always@(posedge CLK or negedge RESET)
begin:TYcounter
if(~RESET)
TimerY<=4'b0101;
else if(St)
TimerY<=4'b0101;
else TimerY<=TimerY-1'b1;
end
assign Ty=TimerY;
always@(CurrentState)
begin
case(CurrentState)
S0:begin
{AG,AY,AR}=3'b100;
{BG,BY,BR}=3'b001;
end
S1:begin
{AG,AY,AR}=3'b010;
{BG,BY,BR}=3'b001;
end 
S2:begin
{AG,AY,AR}=3'b001;
{BG,BY,BR}=3'b100;
end
S3:begin
{AG,AY,AR}=3'b001;
{BG,BY,BR}=3'b010;
end
endcase
end
endmodule

Error (10170): Verilog HDL syntax error at traffic2.v(59) near text "<="; expecting ";", or "@", or "end", or an identifier, or a system task, or "{", or a sequential statement
Error (10149): Verilog HDL Declaration error at traffic2.v(64): identifier "Timer2" is already declared in the present scope

Answer 1

首先，你程序中的EN变量未经过定义；其次， if((EN)&&(Timer2==0))begin:Timer2<=Timer1;Timer<=Timer1;end这里if后面的begin为什么要加冒号？起码在ISE11.1下，这些冒号会导致综合出现错误，你这里报的第一个错指的就是这个。第三，将上面的问题都修改后，语法上就没有问题了，但综合仍然无法通过，ISE11.1提示如下：ERROR:Xst:2089 - "traffic2.v" line 41: This sensitivity list construct will match none of the supported FF or Latch templates.说明你的敏感变量列表设计的有问题，主要问题还是出在这个EN上，建议你修改一下再试

Answer 2

'Error (10149): Verilog HDL Declaration error at traffic2.v(64): identifier "Timer2" is already declared in the present scope 让他变为注释信息试试 在检查一下程序能否运行！！