使用Verilog写task函数时候，却出现下面的报错，请问该怎么解决？

Question

//`timescale 1 ps/ 1 ps

module traffic_lights(
clk,
red,
amber,
green
);

input clk;
output red;
output amber;
output green;

reg red;
reg amber;
reg green;

////dedine the parameter
parameter on=1,
off=0,
red_tics=350,
amber_tics=30,
green_tics=200;
//initial
initial red=off;
initial arber=off;
initial green=off;
///the main progress
always begin
red=on; //打开
light(red,red_tics); //等待
green=on;
light(green,green_tics);
amber=on;
light(amber,amber_tics);
end //类似C语言的函数调用
////define task
task light(color,tics); //定义交通灯的开启时间task
output color; //输出 控制信号
input [31:0] tics; //输入 延时时钟
begin
repeat (tics) @(posedge clock);
color=off;
end
endtask

//// produce the clock
// always @ （posedge clk)
// begin
endmodule

Answer 1

task的格式写法不正确，light后面不需要把端口名加上去。正确如下：task light;output color;input [31:0] tics;beginrepeat (tics) @(posedge clock);endendtask

Answer 2

task 应该不能被综合的吧，只能仿真用的吧