请问有哪位大佬知道该怎么写FPGA实现函数信号发生器的报告吗？

Question

如题所示！

Answer 1

锯齿波VHDL编程源程序：library ieee;use ieee.std_logic.1164.all;entity jvchi2 ispotr(clk2,up_down: in std_logic;dd2:buffer integer range 255 downto 0);end;architecture one of jvchi2 issignal d,temp:integer range 255 downto 0;beginprocess(clk2)beginif(clk2’event and clk2=’1’) thenif temp<198 then temp<=temp+2;else temp<=0;end if;end if;end process;process(temp,up_down)beginif up_down=’0’ then d<=temp;else d<=198-temp;end if;end process;dd2<=d;end;